Along with constant development of semiconductor processes, the three originally independent branches of BIPOLAR, Complementary Metal Oxide Semiconductor (CMOS) and Double-diffused Metal Oxide Semiconductor (DMOS) field effect transistors have been integrated constantly with each other so that the processes of BICMOS into which the BIPOLAR and the CMOS are integrated together and of BCD into which the three are integrated jointly have gradually come into being. With the BCD process into which the BIPOLAR, the CMOS and the DMOS are integrated, the three different types of common processes are integrated: the BIPOLAR is intended for analogy control; the CMOS is intended for digital control; and the DMOS is intended to enable soft startup and power output of a system in the case of the processing of high voltage and large current occurring in management in chip or system. Since respective advantages of the three kinds of devices are integrated in the BCD process, a BCD-based product can be can be integrated with a complex control function so that it has become a predominant process of power integrated circuits. For the BCD process, different devices can be selected for a varying circuit to optimize corresponding sub-circuits, thereby accommodating requirements on low power consumption, high integration, high speed, a high driving capability and large current of the entire circuit.
High voltage MOS transistors in the existing BCD process are primarily Laterally Double-diffused Metal Oxide Semiconductors (LDMOS). FIG. 1 illustrates the steps of forming an LDMOS transistor in the existing BCD process, where a substrate is prepared, the substrate can be made of silicon, silicon-germanium, etc.; boron ions are injected into the substrate to form an N-buried layer area 101; an N-epitaxial layer is formed on the N-buried layer area 101 by an epitaxial method; a first photoresist layer (not illustrated) is formed on the N-epitaxial layer, and an N-well pattern is defined by lithograph process; phosphorus ions are injected into the N-epitaxial layer along the N-well pattern using the first photoresist layer as a mask to form an N-well 102; a second photoresist layer (not illustrated) is formed on the N-epitaxial layer after the first photoresist layer is removed, and a P-well pattern is defined by lithograph process; and phosphorus ions are injected into the N-epitaxial layer along the P-well pattern using the second photoresist layer as a mask to form a P-well 103.
As illustrated in FIG. 2, a LOCal Oxidation of Silicon (LOCOS) isolation area 104 is formed at the interface between the N-well 102 and the P-well 103 by a field oxidation method after the second photoresist layer is removed; a third photoresist layer (not illustrated) is formed on the N-epitaxial layer, and a drift area pattern is defined in the area of the P-well 103 by lithograph process; phosphorus ions are injected into the N-epitaxial layer along the drift area pattern using the third photoresist layer as a mask, and an annealing process is performed to form a drift area 106a; and then the epitaxial layer of the drift area 106a is oxidized in a wet oxygen thermal oxidization method using the third photoresist layer again as a mask to form an LOCOS field plate 106b; and next the third photoresist layer is removed.
As illustrated in FIG. 3, a polysilicon layer and a fourth photoresist layer (not illustrated) are formed sequentially on the N-epitaxial layer, and a gate pattern is defined on the fourth photoresist layer after exposure and development processes; and the polysilicon layer is etched along the gate pattern using the fourth photoresist layer as a mask, a gate 108 is formed on parts of the N-epitaxial layer and the drift area in the area of the P-well 103, and the fourth photoresist layer is removed.
As illustrated in FIG. 4, a fifth photoresist layer (not illustrated) is formed on the N-epitaxial layer, the LOCal Oxidation of Silicon (LOCOS) isolation area 104 and the gate 108, and a PBODY (P-type substrate concentration transition) area pattern is defined on the fifth photoresist layer between the gate 108 in the area of the P-well 103 and the LOCal Oxidation of Silicon (LOCOS) isolation area 104 after the exposure and development processes; and phosphorus ions are injected into the N-epitaxial layer along the PBODY area pattern using the fifth photoresist layer as a mask to form a PBODY area 109, wherein the PBODY 109 functions to form an active channel from a difference between its transverse diffusion length and that of a source/drain to control the threshold voltage of an LDMOS. A sixth photoresist layer (not illustrated) is formed on the N-epitaxial layer, the LOCal Oxidation of Silicon (LOCOS) isolation area 104 and the gate 108 after the fifth photoresist layer is removed, and an opening pattern is defined on the sixth photoresist layer between the drift areas 106 after the exposure and development processes; phosphorus ions are injected into the N-epitaxial layer along the opening pattern using the sixth photoresist layer as a mask, and the annealing process is performed to diffuse uniformly the phosphorus ions into a larger depth so as to form an N-type GRADE (concentration gradient) area 110, wherein the GRADE area functions to form N-type ions with a low concentration outside of the source/drain, to reduce the dope dose of PN junction and to increase the breakdown voltage of the junction. The sixth photoresist layer is removed.
As illustrated in FIG. 5, a seventh photoresist layer (not illustrated) is formed on the N-epitaxial layer, the LOCal Oxidation of Silicon (LOCOS) isolation area 104 and the gate 108, and a source/drain pattern is formed after the exposure and development processes; and phosphorus ions are injected into the PBODY area 109 and the N-type GRADE area 110 in the N-epitaxial layer along the source/drain pattern using the seventh photoresist layer as a mask to form a source S in the PBODY area 109 and a drain D in the N-type GRADE area 110. Further referring to FIG. 5, an eighth photoresist layer (not illustrated) is formed on the N-epitaxial layer, the LOCal Oxidation of Silicon (LOCOS) isolation area 104 and the gate 108 after the seventh photoresist layer is removed, and a P+ area pattern is defined by lithograph process; and boron ions are injected into the PBODY area 109 in the N-epitaxial layer along the P+ area pattern using the eighth photoresist layer as a mask to form a P+ area 112, wherein the P+ area 112 is connected with the source S and functions to prevent a substrate electrode and the source from being shorted and to alleviate a substrate bias effect. Next the eighth photoresist layer is removed.
However since the high voltage MOS transistors in the existing BCD process are primarily LDMOS, there is no possibility to arrange compatibly LDMOS and Vertical Double-diffused Metal Oxide Semiconductor (VDMOS) on the same process platform to accommodate the high voltage-resistance of the LDMOS and the large current driving capability of the VDMOS.